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1 MT9044 t1/e1/oc3 system synchronizer features supports at&t tr62411 and bellcore gr-1244-core stratum 3, stratum 4 enhanced and stratum 4 timing for ds1 interfaces supports itu-t g.813 option 1 clocks for 2048 kbit/s interfaces supports itu-t g.812 type iv clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces supports etsi ets 300 011, tbr 4, tbr 12 and tbr 13 timing for e1 interfaces selectable 1.544mhz, 2.048mhz or 8khz input reference signals provides c1.5, c2, c3, c4, c6, c8, c16, and c19 (sts-3/oc3 clock divided by 8) output clock signals provides 5 different 8khz framing pulses holdover frequency accuracy of 0.05 ppm holdover indication attenuates wander from 1.9hz provides time interval error (tie) correction accepts reference inputs from two independent sources jtag boundary scan applications synchronization and timing control for multitrunk t1,e1 and sts-3/oc3 systems st-bus clock and frame pulse sources description the MT9044 t1/e1/oc3 system synchronizer contains a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links and sts-3/0c3 links. the MT9044 generates st-bus clock and framing signals that are phase locked to either a 2.048mhz, 1.544mhz, or 8khz input reference. the MT9044 is compliant with at&t tr62411 and bellcore gr-1244-core stratum 3, stratum 4 enhanced, and stratum 4; and etsi ets 300 011; and itu-t g.813 option 1 for 2048 kbit/s interfaces. it will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency and mtie requirements for these specifications. ordering information MT9044ap 44 pin plcc MT9044al 44 pin mqfp -40 to +85 c figure 1 - functional block diagram ms1 ms2 gto gti fs1 fs2 tck sec rst rsel los1 los2 vdd vss tclr c3o c1.5o c2o c4o c8o c16o f0o f8o f16o osco osci c19o tdo pri tdi tms trst c6o rsp tsp acki acko holdover output interface circuit frequency select mux master clock apll feedback guard time circuit state select input impairment monitor virtual reference dpll tie corrector circuit state select ieee 1149.1a automatic/manual control state machine reference select mux reference select tie corrector enable selected reference ds5058 issue 5 january 2001
MT9044 2 figure 2 - pin connections pin description pin # plcc pin # mqfp name description 1,10, 23,31 39,4,17 ,25 v ss ground. 0 volts. 2 40 tck test clock (ttl input): provides the clock to the jtag test logic. this pin is internally pulled up to v dd . 341 tclr tie circuit reset (ttl input): a logic low at this input resets the time interval error (tie) correction circuit resulting in a re-alignment of input phase with output phase as shown in figure 19. the tclr pin should be held low for a minimum of 300ns. this pin is internally pulled down to vss. 442 trst test reset (ttl input): asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin is internally pulled down to vss. 5 43 sec secondary reference (ttl input). this is one of two (pri & sec) input reference sources (falling edge) used for synchronization. one of three possible frequencies (8khz, 1.544mhzmhz, or 2.048mhz) may be used. the selection of the input reference is based upon the ms1, ms2, los1, los2, rsel, and gti control inputs (automatic or manual). this pin is internally pulled up to v dd . 6 44 pri primary reference (ttl input). see pin description for sec. this pin is internally pulled up to v dd . 7,28 1,22 v dd positive supply voltage. +5v dc nominal. 8 2 osco oscillator master clock (cmos output). for crystal operation, a 20mhz crystal is connected from this pin to osci, see figure 10. for clock oscillator operation, this pin is left unconnected, see figure 9. 9 3 osci oscillator master clock (cmos input). for crystal operation, a 20mhz crystal is connected from this pin to osco, see figure 10. for clock oscillator operation, this pin is connected to a clock source, see figure 9. 11 5 f16o frame pulse st-bus 8.192 mb/s (cmos output). this is an 8khz 61ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 8.192 mb/s. see figure 20. 1 8 7 43 9 10 11 12 37 33 34 35 36 38 39 40 41 42 vss tclr sec pri vdd osco osci f16o f0o f8o c1.5o gti gto los2 los1 ms2 ms1 rsel fs2 fs1 rst 18 19 20 21 22 23 24 acki vss c8o c16o c4o c19o MT9044ap 2 5 643 44 32 31 30 29 25 26 27 28 13 14 15 16 17 tck trst tms tdi ic vss tdo c2o c6o acko vdd c3o avdd tsp rsp vss holdover 39 2 1 42 41 3 4 5 6 31 27 28 29 30 32 33 34 35 36 vss tclr sec pri vdd osco osci f16o f0o f8o c1.5o gti gto los2 los1 ms2 ms1 rsel fs2 fs1 rst 12 13 14 15 16 17 18 acki vss c8o c16o c4o c19o MT9044al 40 43 44 37 38 26 25 24 19 20 21 22 7 8 9 10 11 tclk trst tms tdi holdover ic vss tdo c2o c6o acko vdd c3o avdd tsp rsp vss 23
MT9044 3 12 6 rsp receive sync pulse (cmos output). this is an 8khz 488ns active high framing pulse, which marks the end of an st-bus frame. this is typically used for connection to the siemens munich-32 device. see figure 21. 13 7 f0o frame pulse st-bus 2.048mb/s (cmos output). this is an 8khz 244ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 2.048mb/s and 4.096mb/s. see figure 20. 14 8 tsp transmit sync pulse (cmos output). this is an 8khz 488ns active high framing pulse, which marks the beginning of an st-bus frame. this is typically used for connection to the siemens munich-32 device. see figure 21. 15 9 f8o frame pulse (cmos output). this is an 8khz 122ns active high framing pulse, which marks the beginning of a frame. see figure 20. 16 10 c1.5o clock 1.544mhz (cmos output). this output is used in t1 applications. 17 11 avdd analog vdd. +5v dc nominal. 18 12 c3o clock 3.088mhz (cmos output). this output is used in t1 applications. 19 13 c2o clock 2.048mhz (cmos output). this output is used for st-bus operation at 2.048mb/s. 20 14 c4o clock 4.096mhz (cmos output). this output is used for st-bus operation at 2.048mb/s and 4.096mb/s. 21 15 c19o clock 19.44mhz (cmos output). this output is used in oc3/sts3 applications. 22 16 acki analog pll clock input (cmos input). this input clock is a reference for an internal analog pll. this pin is internally pulled down to vss. 24 18 acko analog pll clock output (cmos output). this output clock is generated by the internal analog pll. 25 19 c8o clock 8.192mhz (cmos output). this output is used for st-bus operation at 8.192mb/s. 26 20 c16o clock 16.384mhz (cmos output). this output is used for st-bus operation with a 16.384mhz clock. 27 21 c6o clock 6.312 mhz (cmos output). this output is used for ds2 applications. 29 23 holdover holdover (cmos output). this output goes to a logic high whenever the digital pll goes into holdover mode. 30 24 gti guard time (schmitt input). this input is used by the MT9044 state machine in both manual and automatic modes. the signal at this pin affects the state changes between primary holdover mode and primary normal mode, and primary holdover mode and secondary normal mode. the logic level at this input is gated in by the rising edge of f8o. see tables 4 and 5. 32 26 gto guard time (cmos output). the los1 input is gated by the rising edge of f8o, buffered and output on gto. this pin is typically used to drive the gti input through an rc circuit. 33 27 los2 secondary reference loss (ttl input). this input is normally connected to the loss of signal (los) output signal of a line interface unit (liu). when high, the sec reference signal is lost or invalid. los2, along with the los1 and gti inputs control the MT9044 state machine when operating in automatic control. the logic level at this input is gated in by the rising edge of f8o. this pin is internally pulled down to vss. pin description (continued) pin # plcc pin # mqfp name description
MT9044 4 34 28 los1 primary reference loss (ttl input). typically, external equipment applies a logic high to this input when the pri reference signal is lost or invalid. the logic level at this input is gated in by the rising edge of f8o. see los2 description. this pin is internally pulled down to vss. 35 29 tdo test serial data out (ttl output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. 36 30 ms2 mode/control select 2 (ttl input). this input, in conjunction with ms1, determines the devices mode (automatic or manual) and state (normal, holdover or freerun) of operation. the logic level at this input is gated in by the rising edge of f8o. see table 3. 37 31 ms1 mode/control select 1 (ttl input). the logic level at this input is gated in by the rising edge of f8o. see pin description for ms2. this pin is internally pulled down to vss. 38 32 rsel reference source select (ttl input). in manual control, a logic low selects the pri (primary) reference source as the input reference signal and a logic high selects the sec (secondary) input. in automatic control, this pin must be at logic low. the logic level at this input is gated in by the rising edge of f8o. see table 2. this pin is internally pulled down to vss. 39 33 ic internal connection. tie low for normal operation. 40 34 fs2 frequency select 2 (ttl input). this input, in conjunction with fs1, selects which of three possible frequencies (8khz, 1.544mhz, or 2.048mhz) may be input to the pri and sec inputs. see table 1. 41 35 fs1 frequency select 1 (ttl input). see pin description for fs2. 42 36 tdi test serial data in (ttl input). jtag serial test instructions and data are shifted in on this pin. this pin is internally pulled up to v dd . 43 37 rst reset (schmitt input). a logic low at this input resets the MT9044. to ensure proper operation, the device must be reset after changes to the method of control, reference signal frequency changes and power-up. the rst pin should be held low for a minimum of 300ns. while the rst pin is low, all frame and clock outputs are at logic high. following a reset, the input reference source and output clocks and frame pulses are phase aligned as shown in figure 19. 44 38 tms test mode select (ttl input). jtag signal that controls the state transitions of the tap controller. this pin is internally pulled up to v dd . pin description (continued) pin # plcc pin # mqfp name description
MT9044 5 functional description the MT9044 is a multitrunk system synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for t1 and e1 primary rate digital transmission links. figure 1 shows the functional block diagram which is described in the following sections. reference select mux circuit the MT9044 accepts two simultaneous reference input signals and operates on their falling edges. either the primary reference (pri) signal or the secondary reference (sec) signal can be selected as input to the tie corrector circuit. the selection is based on the control, mode and reference selection of the device. see tables 1, 4 and 5. frequency select mux circuit the MT9044 operates with one of three possible input reference frequencies (8khz, 1.544mhz or 2.048mhz). the frequency select inputs (fs1 and fs2) determine which of the three frequencies may be used at the reference inputs (pri and sec). both inputs must have the same frequency applied to them. a reset ( rst) must be performed after every frequency select input change. operation with fs1 and fs2 both at logic low is reserved and must not be used. see table 1. table 1 - input frequency selection time interval error (tie) corrector circuit the tie corrector circuit, when enabled, prevents a step change in phase on the input reference signals (pri or sec) from causing a step change in phase at the input of the dpll block of figure 1. during reference input rearrangement, such as during a switch from the primary reference (pri) to the secondary reference (sec), a step change in phase on the input signals will occur. a phase step at the input of the dpll will lead to unacceptable phase changes in the output signal. as shown in figure 3, the tie corrector circuit receives one of the two reference (pri or sec) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the dpll. therefore, the virtual reference is a delayed version of the selected reference. during a switch, from one reference to the other, the state machine first changes the mode of the device fs2 fs1 input frequency 0 0 reserved 0 1 8khz 1 0 1.544mhz 1 1 2.048mhz figure 3 - tie corrector circuit programmable delay circuit control signal delay value tclr resets delay compare circuit tie corrector enable from state machine control circuit feedback signal from frequency select mux pri or sec from reference select mux virtual reference to dpll
6 MT9044 from normal to holdover. in holdover mode, the dpll no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. the compare circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. this delay value is passed to the programmable delay circuit (see figure 3). the new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch had not taken place. the state machine then returns the device to normal mode. the dpll now uses the new virtual reference signal, and since no phase step took place at the input of the dpll, no phase step occurs at the output of the dpll. in other words, reference switching will not create a phase change at the input of the dpll, or at the output of the dpll. since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the dpll. this phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. each time a reference switch is made, the delay between input signal and output signal will change. the value of this delay is the accumulation of the error measured during each reference switch. the programmable delay circuit can be zeroed by applying a logic low pulse to the tie circuit reset ( tclr) pin. a minimum reset pulse width is 300ns. this results in a phase alignment between the input reference signal and the output signal as shown in figure 20. the speed of the phase alignment correction is limited to 5ns per 125us, and convergence is in the direction of least phase travel. the state diagrams of figure 7 and 8 indicate the state changes that activate the tie corrector circuit. digital phase lock loop (dpll) as shown in figure 4, the dpll of the MT9044 consists of a phase detector, limiter, loop filter, digitally controlled oscillator, and a control circuit. phase detector - the phase detector compares the virtual reference signal from the tie corrector circuit with the feedback signal from the frequency select mux circuit, and provides an error signal corresponding to the phase difference between the two. this error signal is passed to the limiter circuit. the frequency select mux allows the proper feedback signal to be externally selected (e.g., 8khz, 1.544mhz or 2.048mhz). limiter - the limiter receives the error signal from the phase detector and ensures that the dpll responds to all input transient conditions with a maximum output phase slope of 5ns per 125us. this is well within the maximum phase slope of 7.6ns per 125us or 81ns per 1.326ms specified by at&t tr62411, and bellcore gr-1244-core. loop filter - the loop filter is similar to a first order low pass filter with a 1.9 hz cutoff frequency for all three reference frequency selections (8khz, 1.544mhz or 2.048mhz). this filter ensures that the jitter transfer requirements in ets 300 011 and at&t tr62411 are met. control circuit - the control circuit uses status and control information from the state machine and the input impairment circuit to set the mode of the dpll. the three possible modes are normal, holdover and freerun. digitally controlled oscillator (dco) - the dco receives the limited and filtered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchronization method of the dco is dependent on the state of the MT9044. figure 4 - dpll block diagram limiter loop filter digitally controlled oscillator phase detector feedback signal from frequency select mux state select from input impairment monitor state select from state machine dpll reference to output interface circuit virtual reference from tie corrector control circuit
MT9044 7 in normal mode, the dco provides an output signal which is frequency and phase locked to the selected input reference signal. in holdover mode, the dco is free running at a frequency equal to the last (less 30ms to 60ms) frequency the dco was generating while in normal mode. in freerun mode, the dco is free running with an accuracy equal to the accuracy of the osci 20mhz source. output interface circuit the output of the dco (dpll) is used by the output interface circuit to provide the output signals shown in figure 5. the output interface circuit uses four tapped delay lines followed by a t1 divider circuit , an e1 divider circuit, a ds2 divider circuit and an analog pll to generate the required output signals. four tapped delay lines are used to generate a 16.384mhz, 12.352mhz, 12.624mhz and 19.44 mhz signals. the e1 divider circuit uses the 16.384mhz signal to generate four clock outputs and three frame pulse outputs. the c8o, c4o and c2o clocks are generated by simply dividing the c16o clock by two, four and eight respectively. these outputs have a nominal 50% duty cycle. the t1 divider circuit uses the 12.384mhz signal to generate two clock outputs. c1.5o and c3o are generated by dividing the internal c12 clock by four and eight respectively. these outputs have a nominal 50% duty cycle. the ds2 divider circuit uses the 12.624 mhz signal to generate the clock output c6o. this output has a nominal 50% duty cycle. figure 5 - output interface circuit block diagram the frame pulse outputs ( f0o, f8o, f16o, tsp, rsp) are generated directly from the c16 clock. the t1 and e1 signals are generated from a common dpll signal. consequently, the clock outputs c1.5o, c3o, c2o, c4o, c8o, c16o, f0o, f16o and c6o are locked to one another for all operating states, and are also locked to the selected input reference in normal mode. see figures 20 and 21. all frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g. 30pf) loads. analog phase lock loop (apll) the analog pll is intended to be used to achieve a 50% duty cycle output clock. connecting c19o to acki will generate a phase locked 19.44 mhz acko output with a nominal 50% duty cycle and a maximum peak_to_peak unfiltered jitter of 0.174 u.i. . the analog pll has an intrinsic jitter of less than 0.01 u.i. in order to achieve this low jitter level a separate pin is provided to power (avdd) the analog pll. tapped delay line from dpll t1 divider e1 divider 16mhz 12mhz c3o c1.5o c2o c4o c8o c16o f0o f8o f16o tapped delay line tapped delay line tapped delay line analog pll ds2 divider 12mhz 19mhz c6o c19o acko acki
MT9044 8 input impairment monitor this circuit monitors the input signal to the dpll and automatically enables the holdover mode (auto-holdover) when the frequency of the incoming signal is outside the auto-holdover capture range (see ac electrical characteristics - performance). this includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. when the incoming signal returns to normal, the dpll is returned to normal mode with the output signal locked to the input signal. the holdover output signal is based on the incoming signal 30ms minimum to 60ms prior to entering the holdover mode. the amount of phase drift while in holdover is negligible because the holdover mode is very accurate (e.g. 0.05ppm). the the auto-holdover circuit does not use tie correction. consequently, the phase delay between the input and output after switching back to normal mode is preserved (is the same as just prior to the switch to auto-holdover). automatic/manual control state machine the automatic/manual control state machine allows the MT9044 to be controlled automatically (i.e. los1, los2 and gti signals) or controlled manually (i.e. ms1, ms2, gti and rsel signals). with manual control a single mode of operation (i.e. normal, holdover and freerun) is selected. under automatic control the state of the los1, los2 and gti signals determines the sequence of modes that the MT9044 will follow. as shown in figure 1, this state machine controls the reference select mux, the tie corrector circuit, the dpll and the guard time circuit. control is based on the logic levels at the control inputs los1, los2, rsel, ms1, ms2 and gti of the guard time circuit (see figure 6). all state machine changes occur synchronously on the rising edge of f8o. see the controls and modes of operation section for full details on automatic control and manual control. figure 6 - automatic/manual control state machine block diagram guard time circuit the gti pin is used by the automatic/manual control state machine in the MT9044 under either manual or automatic control. the logic level at the gti pin performs two functions, it enables and disables the tie corrector circuit (manual and automatic), and it selects which mode change takes place (automatic only). see the applications - guard time section. for both manual and automatic control, when switching from primary holdover to primary normal, the tie corrector circuit is enabled when gti=1, and disabled when gti=0. under automatic control and in primary normal mode, two state changes are possible (not counting auto-holdover). these are state changes to primary holdover or to secondary normal. the logic level at the gti pin determines which state change occurs. when gti=0, the state change is to primary holdover. when gti=1, the state change is to secondary normal. master clock the MT9044 can use either a clock or crystal as the master timing source. for recommended master timing circuits, see the applications - master clock section. control and modes of operation the MT9044 can operate either in manual or automatic control. each control method has three possible modes of operation, normal, holdover and freerun. as shown in table 3, mode/control select pins ms2 and ms1 select the mode and method of control. ms1 ms2 to reference select mux to tie corrector enable automatic/manual control state machine to dpll state select rsel los1 los2 to and from guard time circuit control rsel input reference manual 0 pri 1 sec auto 0 state machine control 1 reserved table 2 - input reference selection
MT9044 9 manual control manual control should be used when either very simple MT9044 control is required, or when complex control is required which is not accommodated by automatic control. for example, very simple control could include operation in a system which only requires normal mode with reference switching using only a single input stimulus (rsel). very simple control would require no external circuitry. complex control could include a system which requires state changes between normal, holdover and freerun modes based on numerous input stimuli. complex control would require external circuitry, typically a microcontroller. under manual control, one of the three modes is selected by mode/control select pins ms2 and ms1. the active reference input (pri or sec) is selected by the rsel pin as shown in table 2. refer to table 4 and figure 7 for details of the state change sequences. automatic control automatic control should be used when simple MT9044 control is required, which is more complex than the very simple control provide by manual control with no external circuitry, but not as complex as manual control with a microcontroller. for example, simple control could include operation in a system which can be accommodated by the automatic control state diagram shown in figure 8. automatic control is also selected by mode/control pins ms2 and ms1. however, the mode and active reference source is selected automatically by the internal automatic state machine (see figure 6). the mode and reference changes are based on the logic levels on the los1, los2 and gti control pins. refer to table 5 and figure 8 for details of the state change sequences. normal mode normal mode is typically used when a slave clock source, synchronized to the network is required. in normal mode, the MT9044 provides timing (c1.5o, c2o, c3o, c4o, c8o, c16o , and c19) and frame synchronization ( f0o, f8o, f16o, rsp, tsp) signals, which are synchronized to one of two reference inputs (pri or sec). the input reference signal may have a nominal frequency of 8khz, 1.544mhz or 2.048mhz. from a reset condition, the MT9044 will take up to 25 seconds for the output signal to be phase locked to the selected reference. the selection of input references is control dependent as shown in state tables 4 and 5. the reference frequencies are selected by the frequency control pins fs2 and fs1 as shown in table 1. holdover mode holdover mode is typically used for short durations (e.g. 2 seconds) while network synchronization is temporarily disrupted. in holdover mode, the MT9044 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. the storage value is determined while the device is in normal mode and locked to an external reference signal. when in normal mode, and locked to the input reference signal, a numerical value corresponding to the MT9044 output frequency is stored alternately in two memory locations every 30ms. when the device is switched into holdover mode, the value in memory from between 30ms and 60ms is used to set the output frequency of the device. the frequency accuracy of holdover mode is 0.05ppm, which translates to a worst case 35 frame (125us) slips in 24 hours. this meets the bellcore gr-1244-core stratum 3 requirement of 0.37ppm (255 frame slips per 24 hours). two factors affect the accuracy of holdover mode. one is drift on the master clock while in holdover mode, drift on the master clock directly affects the holdover mode accuracy. note that the absolute master clock (osci) accuracy does not affect holdover accuracy, only the change in osci accuracy while in holdover. for example, a 32ppm ms2 ms1 control mode 0 0 manual normal 0 1 manual holdover 1 0 manual freerun 1 1 auto state machine control table 3 - operating modes and states
MT9044 10 master clock may have a temperature coefficient of 0.1ppm per degree c. so a 10 degree change in temperature, while the MT9044 is in holdover mode may result in an additional offset (over the 0.05ppm) in frequency accuracy of 1ppm, which is much greater than the 0.05ppm of the MT9044. the other factor affecting accuracy is large jitter on the reference input prior (30ms to 60ms) to the mode switch. for instance, jitter of 7.5ui at 700hz may reduce the holdover mode accuracy from 0.05ppm to 0.10ppm. freerun mode freerun mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. in freerun mode, the MT9044 provides timing and synchronization signals which are based on the master clock frequency (osci) only, and are not synchronized to the reference signals (pri and sec). the accuracy of the output clock is equal to the accuracy of the master clock (osci). so if a 32ppm output clock is required, the master clock must also be 32ppm. see applications - crystal and clock oscillator sections.
MT9044 11 figure 7 - manual control state diagram description state input controls freerun normal (pri) normal (sec) holdover (pri) holdover (sec) ms2 ms1 rsel gti s0 s1 s2 s1h s2h 0 0 0 0 s1 - s1 mtie s1 s1 mtie 0 0 0 1 s1 - s1 mtie s1 mtie s1 mtie 0 0 1 x s2 s2 mtie - s2 mtie s2 mtie 0 1 0 x / s1h / - / 0 1 1 x / s2h s2h / - 10 x x - s0 s0 s0 s0 legend: - no change / not valid mtie state change occurs with tie corrector circuit refer to manual control state diagram for state changes to and from auto-holdover state table 4 - manual control state table phase re-alignment phase continuity maintained (without tie corrector circuit) phase continuity maintained (with tie corrector circuit) notes: (xxx) ms2 ms1 rsel {a} invalid reference signal movement to normal state from any state requires a valid input signal {a} {a} s0 freerun (10x) s2h holdover secondary (011) s1h holdover primary (010) s2 normal secondary (001) s1 normal primary (000) (gti=0) (gti=1) s1a auto-holdover primary (000) s2a auto-holdover secondary (001)
MT9044 12 figure 8 - automatic control state diagram description state input controls freerun normal (pri) normal (sec) holdover (pri) holdover (sec) los2 los1 gti rst s0 s1 s2 s1h s2h 1 1 x 0 to 1 - s0 s0 s0 s0 x 0 0 1 s1 - s1 mtie s1 s1 mtie x 0 1 1 s1 - s1 mtie s1 mtie s1 mtie 0 1 0 1 s1 s1h - - s2 mtie 0 1 1 1 s2 s2 mtie - s2 mtie s2 mtie 1 1 x 1 - s1h s2h - - legend: - no change mtie state change occurs with tie corrector circuit refer to automatic control state diagram for state changes to and from auto-holdover state table 5 - automatic control (ms1=ms2=1, rsel=0) state table (01x) (x0x) (01x) (x0x) {a} (11x) (011) (11x) (011) (x0x) (11x) (01x) (01x) (010 or 11x) (x0x) (x0x) (01x) (x01) reset {a} s0 freerun s2h holdover secondary s1h holdover primary s2 normal secondary s1 normal primary (x00) s1a auto-holdover primary s2a auto-holdover secondary (010 or 11x) (11x) rst=1 (x0x) notes: (xxx) los2 los1 gti {a} invalid reference signal movement to normal state from any state requires a valid input signal phase re-alignment phase continuity maintained (without tie corrector circuit) phase continuity maintained (with tie corrector circuit)
MT9044 13 MT9044 measures of performance the following are some synchronizer performance indicators and their corresponding definitions. intrinsic jitter intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. jitter tolerance jitter tolerance is a measure of the ability of a pll to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. the applied jitter magnitude and jitter frequency depends on the applicable standards. jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. for the MT9044, two internal elements determine the jitter attenuation. this includes the internal 1.9hz low pass loop filter and the phase slope limiter. the phase slope limiter limits the output phase slope to 5ns/125us. therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e. attenuated) to 5ns/125us. the MT9044 has thirteen outputs with three possible input frequencies for a total of 39 possible jitter transfer functions. however, the data sheet section on ac electrical characteristics - jitter transfer specifies transfer values for only three cases, 8khz to 8khz, 1.544mhz to 1.544mhz and 2.048mhz to 2.048mhz. since all outputs are derived from the same signal, these transfer values apply to all outputs. it should be noted that 1ui at 1.544mhz is 644ns, which is not equal to 1ui at 2.048mhz, which is 488ns. consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g. seconds) as shown in the following example. what is the t1 and e1 output jitter when the t1 input jitter is 20ui (t1 ui units) and the t1 to t1 jitter attenuation is 18db? using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. note that the resulting jitter transfer functions for all combinations of inputs (8khz, 1.544mhz, 2.048mhz) and outputs (8khz, 1.544mhz, 2.048mhz, 4.096mhz, 8.192mhz, 16.384mhz) for a given input signal (jitter frequency and jitter amplitude) are the same. since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g. 75% of the specified maximum jitter tolerance). frequency accuracy frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. for the MT9044, the freerun accuracy is equal to the master clock (osci) accuracy. holdover accuracy holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. for the MT9044, outputt 1 inputt 1 a 20 ------ - ?? ?? 10 = outputt 120 18 20 -------- - ?? ?? 10 2.5 ui t 1 () == outpute 1 outputt 1 644 ns () 488 ns () ------------------- 3.3 ui t 1 () = = outpute 1 outputt 1 1 uit 1 () 1 uie 1 () --------------------- - =
MT9044 14 the storage value is determined while the device is in normal mode and locked to an external reference signal. the absolute master clock (osci) accuracy of the MT9044 does not affect holdover accuracy, but the change in osci accuracy while in holdover mode does. capture range also referred to as pull-in range. this is the input frequency range over which the synchronizer must be able to pull into synchronization. the MT9044 capture range is equal to 230ppm minus the accuracy of the master clock (osci). for example, a 32ppm master clock results in a capture range of 198ppm. lock range this is the input frequency range over which the synchronizer must be able to maintain synchronization. the lock range is equal to the capture range for the MT9044. phase slope phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. the given signal is typically the output signal. the ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. time interval error (tie) tie is the time delay between a given timing signal and an ideal timing signal. maximum time interval error (mtie) mtie is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. phase continuity phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. usually, the given timing signal and the ideal timing signal are of the same frequency. phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a mode change. the observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. in the case of the MT9044, the output signal phase continuity is maintained to within 5ns at the instance (over one frame) of all reference switches and all mode changes. the total phase shift, depending on the switch or type of mode change, may accumulate up to 200ns over many frames. the rate of change of the 200ns phase shift is limited to a maximum phase slope of approximately 5ns/125us. this meets the maximum phase slope requirement of bellcore gr-1244-core (81ns/ 1.326ms). phase lock time this is the time it takes the synchronizer to phase lock to the input signal. phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) synchronizer loop filter iv) synchronizer limiter although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. for instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. and better (smaller) phase slope performance (limiter) results in longer lock times. the MT9044 loop filter and limiter were optimized to meet the at&t tr62411 jitter transfer and phase slope requirements. consequently, phase lock time, which is not a standards requirement, may be longer than in other applications. see ac electrical characteristics - performance for maximum phase lock time. mtie s () tiemax t () tiemin t () =
MT9044 15 MT9044 and network specifications the MT9044 fully meets all applicable pll requirements (intrinsic jitter/wander, jitter/wander tolerance, jitter/wander transfer, frequency accuracy, frequency holdover accuracy, capture range, phase change slope and mtie during reference rearrangement) for the following specifications. 1. bellcore gr-1244-core june 1995 for stratum 3, stratum 4 enhanced and stratum 4 2. at&t tr62411 (ds1) december 1990 for stratum 3, stratum 4 enhanced and stratum 4 3. ansi t1.101 (ds1) february 1994 for stratum 3, stratum 4 enhanced and stratum 4 4. etsi 300 011 (e1) april 1992 for single access and multi access 5. tbr 4 november 1995 6. tbr 12 december 1993 7. tbr 13 january 1996 8. itu-t i.431 march 1993 9. itu-t g.813 august 1996 for option1 clocks for 2048 kbit/s interfaces 10. itu-t g.812 june 1998 for type iv clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces applications this section contains MT9044 application specific details for clock and crystal operation, guard time usage, reset operation, power supply decoupling, manual control operation and automatic control operation. master clock the MT9044 can use either a clock or crystal as the master timing source. in freerun mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the osci pin. for applications not requiring an accurate freerun mode, tolerance of the master timing source may be 100ppm. for applications requiring an accurate freerun mode, such as bellcore gr-1244-core, the tolerance of the master timing source must be no greater than 32ppm. another consideration in determining the accuracy of the master timing source is the desired capture range. the sum of the accuracy of the master timing source and the capture range of the MT9044 will always equal 230ppm. for example, if the master timing source is 100ppm, then the capture range will be 130ppm. clock oscillator - when selecting a clock oscillator, numerous parameters must be considered. this includes absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle. see ac electrical characteristics. figure 9 - clock oscillator circuit for applications requiring 32ppm clock accuracy, the following clock oscillator module may be used. +5v 20mhz out gnd 0.1uf +5v osco MT9044 osci no connection
MT9044 16 cts cxo-65-hg-5-c-20.0mhz frequency: 20mhz tolerance: 25ppm 0c to 70c rise & fall time: 8ns (0.5v 4.5v 50pf) duty cycle: 45% to 55% the output clock should be connected directly (not ac coupled) to the osci input of the MT9044, and the osco output should be left open as shown in figure 9. crystal oscillator - alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistor and capacitors is shown in figure 10. figure 10 - crystal oscillator circuit the accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. typically, for a 20mhz crystal specified with a 32pf load capacitance, each 1pf change in load capacitance contributes approximately 9ppm to the frequency deviation. consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. the trimmer capacitor shown in figure 10 may be used to compensate for capacitive effects. if accuracy is not a concern, then the trimmer may be removed, the 39pf capacitor may be increased to 56pf, and a wider tolerance crystal may be substituted. the crystal should be a fundamental mode type - not an overtone. the fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. the crystal specification is as follows. frequency: 20mhz tolerance: as required oscillation mode: fundamental resonance mode: parallel load capacitance: 32pf maximum series resistance: 35 ? approximate drive level: 1mw e.g., cts r1027-2bb-20.0mhz ( 20ppm absolute, 6ppm 0c to 50c, 32pf, 25 ? ) guard time adjustment excessive switching of the timing reference (from pri to sec) in the MT9044 can be minimized by first entering holdover mode for a predetermined maximum time (i.e., guard time). if the degraded signal returns to normal before the expiry of the guard time (e.g. 2.5 seconds), then the MT9044 is returned to its normal mode (with no reference switch taking place). otherwise, the reference input may be changed from primary to secondary. figure 11 - symmetrical guard time circuit a simple way to control the guard time (using automatic control) is with an rc circuit as shown in figure 11. resistor r p is for protection only and limits the current flowing into the gti pin during power down conditions. the guard time can be calculated as follows. ? sih is the logic high going threshold level for the gti schmitt trigger input, see dc electrical characteristics in cases where fast toggling might be expected of the los1 input, then an unsymmetrical guard time circuit is recommended. this ensures that reference switching doesn? occur until the full guard time value osco 56pf 1m ? 39pf 3-50pf 20mhz MT9044 osci 100 ? 1uh 1uh inductor: may improve stability and is optional gti c 10uf r 150k ? MT9044 gto + r p 1k ? guard time rc v dd v dd v sih --------------------------------- - ?? ?? ?? ln = guard time rc 0.6 guard time 150 k 10 u 0.6 0.9 s = example
MT9044 17 has expired. an unsymmetrical guard time circuit is shown in figure 12. figure 12 - unsymmetrical guard time circuit figure 13 shows a typical timing example of an unsymmetrical guard time circuit with the MT9044 in automatic control. tie correction (using gti) when primary holdover mode is entered for short time periods, tie correction should not be enabled. this will prevent unwanted accumulated phase change between the input and output. this is mainly applicable to manual control, since automatic control together with the guard time circuit inherently operate in this manner. for instance, 10 normal to holdover to normal mode change sequences occur, and in each case holdover was entered for 2s. each mode change sequence could account for a phase change as large as 350ns. thus, the accumulated phase change could be as large as 3.5us, and, the overall mtie could be as large as 3.5us. 0.05ppm is the accuracy of holdover mode 50ns is the maximum phase continuity of the MT9044 from normal mode to holdover mode 200ns is the maximum phase continuity of the MT9044 from holdover mode to normal mode (with or without tie corrector circuit) when 10 normal to holdover to normal mode change sequences occur without mtie enabled, and in each case holdover was entered for 2s, each mode change sequence could still account for a phase change as large as 350ns. however, there would be no accumulated phase change, since the input to output phase is re-aligned after every holdover to normal state change. the overall mtie would only be 350ns. r p 1k ? gti c 10uf r c 150k ? MT9044 gto + r d 1k ? phase hold 0.05 ppm 2 s 100 ns == phase state 50 ns 200 ns 250 ns = + = phase 10 10 250 ns 100 ns + () 3.5 us == figure 13 - automatic control, unsymmetrical guard time circuit timing example pri normal sec normal pri holdover pri normal los2 good pri signal status sec signal status los1 pri normal pri holdover bad good bad good good gto gti MT9044 state v sih notes: 1. t d represents the time delay from when the reference goes bad to when the MT9044 is provided with a los indication. t d t d
18 MT9044 reset circuit a simple power up reset circuit with about a 50us reset low time is shown in figure 14. resistor r p is for protection only and limits current into the rst pin during power down conditions. the reset low time is not critical but should be greater than 300ns. figure 14 - power-up reset circuit dual t1 reference sources with MT9044 in automatic control for systems requiring simple state machine control, the application circuit shown in figure 15 using automatic control may be used. in this circuit, the MT9044 is operating automatically, using a guard time circuit, and the los1 and los2 inputs to determine all mode changes. since the guard time circuit is set to about 1s, all line interruptions (los1=1) less than 1s will cause the MT9044 to go from primary normal mode to holdover mode and not switch references. for line interruptions greater than 1s, the MT9044 will switch modes from holdover to secondary normal, provided that the secondary signal is valid (los2=0). after receiving a good primary signal (los1=0), the MT9044 will switch back to primary normal mode for complete automatic control state machine details, refer to table 5 for the state table, and figure 8 for the state diagram. +5v rst r p 1k ? c 10nf r 10k ? MT9044 figure 15 - dual t1 reference sources with MT9044 in 1.544mhz automatic control 1k ? 1k ? 10nf to tx line xfmr mt8985 sto0 sti0 sto1 sti1 f0i c4i MT9044 f0o c4o fs1 gto fs2 gti pri sec los1 los2 osci ms1 ms2 rsel to rx line xfmr to line 1 out mt9074 to tx line xfmr dsto dsti f0i c4i ttip tring rtip rring los e1.5o to rx line xfmr to line 2 10uf 150k ? rst trst 10k ? + mt9074 dsto dsti f0i c4i ttip tring rtip rring los e1.5o 20mhz 32ppm clock 1k ? + 5v + 5v + 5v
MT9044 19 dual e1 reference sources with MT9044 in manual control for systems requiring complex state machine control, the application circuit shown in figure 16 using manual control may be used. in this circuit, the MT9044 is operating manually and is using a controller for all mode changes. the controller sets the MT9044 modes (normal, holdover or freerun) by controlling the MT9044 mode/control select pins (ms2 and ms1). the input (primary or secondary) is selected with the reference select pin (rsel). tie correction from primary holdover mode to primary normal mode is enabled and disabled with the guard time input pin (gti). the input to output phase alignment is re-aligned with the tie circuit reset pin ( tclr), and a complete device reset is done with the rst pin. the controller uses two stimulus inputs (los) directly from the mt9075 e1 interfaces, as well as an external stimulus input. the external input may come from a device that monitors the status registers of the e1 interfaces, and outputs a logic one in the event of an unacceptable status condition. for complete manual control state machine details, refer to table 4 for the state table, and figure 7 for the state diagram. figure 16 - dual e1 reference sources with MT9044 in 8khz manual control controller to tx line xfmr mt8985 sto0 sti0 sto1 sti1 f0i c4i MT9044 f0o c4o c1.5o fs1 fs2 gti pri sec los1 los2 osci ms1 ms2 rsel to rx line xfmr to line 1 to tx line xfmr to rx line xfmr to line 2 rst trst mt9075 dsto dsti f0i c4i rxfp ttip tring rtip rring los external stimulus mt9075 dsto dsti f0i c4i rxfp ttip tring rtip rring los out 20mhz 32ppm clock + 5v
MT9044 20 single reference source e1 to sts-3 with 8 khz reference the device may operate in freerun mode or with a single reference source. the 8 khz output from the mt9075 is sourced from the clock extracted from the e1 trunk. it becomes the reference for the pll which then generates st-bus signals f0o, c4o and c2o to form the system backplane clock. the mt90840 connects to the system backplane, as well as to an oc3 link via an sts-3 framer and optical link. the 19.44 mhz clock required by the mt90840 is generated by the MT9044. in the event that the e1 link is broken, the los output of the mt9075 goes high placing the MT9044 in freerun mode. figure 17 - single source - e1 to sts-3 with 8khz reference to tx line xfmr mt90820 sto0 sti0 sto1-8 sti1-8 f0i c4i MT9044 f0o c4o c1.5o fs1 fs2 gti pri los1 los2 osci ms1 ms2 rsel to rx line xfmr to e1 line to tx line xfmr to rx line xfmr to oc3 line rst tclr mt9075 dsto dsti f0i c4i rxfp ttip tring rtip rring los mt90840 sto0-7 sti0-7 f0i c4b pdo0-7 pdi0-7 pckr out 20mhz 32ppm clock + 5v pckt ppfri c19o 1k ? 10nf 10k ? + 5v ppfto acki acko
MT9044 21
MT9044 22 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * supply voltage and operating temperature are as per recommended operating conditions. absolute maximum ratings* - voltages are with respect to ground (vss) unless otherwise stated parameter symbol min max units 1 supply voltage v dd -0.3 7.0 v 2 voltage on any pin v pin -0.3 v dd +0.3 v 3 current on any pin i pin 20 ma 4 storage temperature t st -55 125 c 5 plcc package power dissipation p pd 900 mw 6 mqfp package power dissipation p pd 900 mw recommended operating conditions* - * voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym min max units 1 supply voltage v dd 4.5 5.5 v 2 operating temperature t a -40 85 c dc electrical characteristics* - * voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym min max units conditions/notes 1 supply current with: osci = 0v i dds 10 ma outputs unloaded 2 osci = clock i dd 90 ma outputs unloaded 3 ttl high-level input voltage v ih 2.0 v 4 ttl low-level input voltage v il 0.8 v 5 cmos high-level input voltage v cih 0.7v dd v osci 6 cmos low-level input voltage v cil 0.3v dd v osci 7 schmitt high-level input voltage v sih 2.3 v gti, rst 8 schmitt low-level input voltage v sil 0.8 v gti, rst 9 schmitt hysteresis voltage v hys 0.4 v gti, rst 10 input leakage current i il -10 +10 a v i =v dd or 0v 11 high-level output voltage v oh 2.4v v i oh =10ma 12 low-level output voltage v ol 0.4v v i ol =10ma
MT9044 23 ? see "notes" following ac electrical characteristics tables. * supply voltage and operating temperature are as per recommended operating conditions. * timing for input and output signals is based on the worst case result of the combination of ttl and cmos thresholds. * see figure 18. figure 19 - timing parameter measurement voltage levels ac electrical characteristics - performance characteristics sym min max units conditions/notes ? 1 freerun mode accuracy with osci at: 0ppm -0 +0 ppm 5-8 2 32ppm -32 +32 ppm 5-8 3 100ppm -100 +100 ppm 5-8 4 holdover mode accuracy with osci at: 0ppm -0.05 +0.05 ppm 1,2,4,6-8,40 5 32ppm -0.05 +0.05 ppm 1,2,4,6-8,40 6 100ppm -0.05 +0.05 ppm 1,2,4,6-8,40 7 capture range with osci at: 0ppm -230 +230 ppm 1-3,6-8 8 32ppm -198 +198 ppm 1-3,6-8 9 100ppm -130 +130 ppm 1-3,6-8 10 phase lock time 30 s 1-3,6-14 11 output phase continuity with: reference switch 200 ns 1-3,6-14 12 mode switch to normal 200 ns 1-2,4-14 13 mode switch to freerun 200 ns 1-,4,6-14 14 mode switch to holdover 50 ns 1-3,6-14 15 mtie (maximum time interval error) 600 ns 1-14,27 16 output phase slope 45 us/s 1-14,27 17 reference input for auto-holdover with: 8khz -18k +18k ppm 1-3,6,9-11 18 1.544mhz -36k +36k ppm 1-3,7,9-11 19 2.048mhz -36k +36k ppm 1-3,8-11 ac electrical characteristics - timing parameter measurement voltage levels* - voltages are with respect to ground (vss) unless otherwise stated characteristics sym schmitt ttl cmos units 1 threshold voltage v t 1.5 1.5 0.5v dd v 2 rise and fall threshold voltage high v hm 2.3 2.0 0.7v dd v 3 rise and fall threshold voltage low v lm 0.8 0.8 0.3v dd v t irf, t orf timing reference points all signals v hm v t v lm t irf, t orf
MT9044 24 ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - input/output timing characteristics sym min max units 1 reference input pulse width high or low t rw 100 ns 2 reference input rise or fall time t irf 10 ns 3 8khz reference input to f8o delay t r8d -21 6 ns 4 1.544mhz reference input to f8o delay t r15d 337 363 ns 5 2.048mhz reference input to f8o delay t r2d 222 238 ns 6 f8o to f0o delay t f0d 110 134 ns 7 f16o setup to c16o f alling t f16s 11 35 ns 8 f16o hold from c16o rising t f16h 020ns 9 f8o to c1.5o delay t c15d -51 -37 ns 10 f8o to c6o delay t c6d -3 11 ns 11 f8o to c3o delay t c3d -51 -37 ns 12 f8o to c2o delay t c2d -13 2 ns 13 f8o to c4o delay t c4d -13 2 ns 14 f8o to c8o delay t c8d -13 2 ns 15 f8o to c16o delay t c16d -13 2 ns 16 f8o to tsp delay t tspd -10 10 ns 17 f8o to rsp delay t rspd -10 10 ns 18 f8o to c19o delay t c19d 052ns 19 c1.5o pulse width high or low t c15w 309 339 ns 20 c3o pulse width high or low t c3w 149 175 ns 21 c6o pulse width high or low t c6w 72 86 ns 22 c2o pulse width high or low t c2w 230 258 ns 23 c4o pulse width high or low t c4w 111 133 ns 24 c8o pulse width high or low t c8w 52 70 ns 25 c16o pulse width high or low t c16wl 24 35 ns 26 tsp pulse width high t tspw 478 494 ns 27 rsp pulse width high t rspw 474 491 ns 28 c19o pulse width high or low t c19w 16 36 ns 29 f0o pulse width low t f0wl 230 258 ns 30 f8o pulse width high t f8wh 111 133 ns 31 f16o pulse width low t f16wl 52 70 ns 32 output clock and frame pulse rise or fall time t orf 9ns 33 input controls setup time t s 100 ns 34 input controls hold time t h 100 ns
MT9044 25 figure 20 - input to output timing (normal mode) figure 21 - output timing 1 t rw t r15d t r2d t r8d f8o notes: 1. input to output delay values are valid after a trst or rst with no further state changes v t v t v t v t pri/sec 8khz pri/sec 2.048mhz pri/sec 1.544mhz t rw t rw t f16wl t f8wh t c15w t c15d t c3d t c4d t c16d t c8d t f16s t f0d f0o f16o c16o c8o c4o c2o c3o c1.5o t c2d f8o t c4w t f0wl t c16wl t c8w t c2w t c3w t c8w t c4w t c3w v t v t v t v t v t v t v t v t v t t c19w c19o t c19d t c6d t c6w t c6w c6o v t v t t f16h
MT9044 26 figure - 22 output timing 2 figure 23 - input controls setup and hold timing ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - intrinsic jitter un?tered characteristics sym min max units conditions/notes? 1 intrinsic jitter at f8o (8khz) 0.0002 uipp 1-14,21-24,28 2 intrinsic jitter at f0o (8khz) 0.0002 uipp 1-14,21-24,28 3 intrinsic jitter at f16o (8khz) 0.0002 uipp 1-14,21-24,28 4 intrinsic jitter at c1.5o (1.544mhz) 0.030 uipp 1-14,21-24,29 5 intrinsic jitter at c2o (2.048mhz) 0.040 uipp 1-14,21-24,30 6 intrinsic jitter at c3o (3.088mhz) 0.060 uipp 1-14,21-24,31 7 intrinsic jitter at c6o (6.312mhz) 0.120 uipp 1-14,21-24,31 8 intrinsic jitter at c4o (4.096mhz) 0.080 uipp 1-14,21-24,32 9 intrinsic jitter at c8o (8.192mhz) 0.160 uipp 1-14,21-24,33 10 intrinsic jitter at c16o (16.384mhz) 0.320 uipp 1-14,21-24,34 11 intrinsic jitter at tsp (8khz) 0.0002 uipp 1-14,21-24,28 12 intrinsic jitter at rsp (8khz) 0.0002 uipp 1-14,21-24,28 13 intrinsic jitter at c19o (19.44mhz) 0.23 uipp 1-14,21-24,41 t rspd t tspd tsp c2o t tspw t rspw v t v t v t v t rsp f8o t h t s f8o ms1,2 los1,2 rsel, gti v t v t
MT9044 27 ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - c1.5o (1.544mhz) intrinsic jitter filtered characteristics sym min max units conditions/notes? 1 intrinsic jitter (4hz to 100khz ?ter) 0.015 uipp 1-14,21-24,29 2 intrinsic jitter (10hz to 40khz ?ter) 0.010 uipp 1-14,21-24,29 3 intrinsic jitter (8khz to 40khz ?ter) 0.010 uipp 1-14,21-24,29 4 intrinsic jitter (10hz to 8khz ?ter) 0.005 uipp 1-14,21-24,29 ac electrical characteristics - c2o (2.048mhz) intrinsic jitter filtered characteristics sym min max units conditions/notes? 1 intrinsic jitter (4hz to 100khz ?ter) 0.015 uipp 1-14,21-24,30 2 intrinsic jitter (10hz to 40khz ?ter) 0.010 uipp 1-14,21-24,30 3 intrinsic jitter (8khz to 40khz ?ter) 0.010 uipp 1-14,21-24,30 4 intrinsic jitter (10hz to 8khz ?ter) 0.005 uipp 1-14,21-24,30 ac electrical characteristics - 8khz input to 8khz output jitter transfer characteristics sym min max units conditions/notes? 1 jitter attenuation for 1hz@0.01uipp input 0 6 db 1-3,6,9-14,21-22,24,28,35 2 jitter attenuation for 1hz@0.54uipp input 6 16 db 1-3,6,9-14,21-22,24,28,35 3 jitter attenuation for 10hz@0.10uipp input 12 22 db 1-3,6,9-14,21-22,24,28,35 4 jitter attenuation for 60hz@0.10uipp input 28 38 db 1-3,6,9-14,21-22,24,28,35 5 jitter attenuation for 300hz@0.10uipp input 42 db 1-3,6,9-14,21-22,24,28,35 6 jitter attenuation for 3600hz@0.005uipp input 45 db 1-3,6,9-14,21-22,24,28,35 ac electrical characteristics - 1.544mhz input to 1.544mhz output jitter transfer characteristics sym min max units conditions/notes? 1 jitter attenuation for 1hz@20uipp input 0 6 db 1-3,7,9-14,21-22,24,29,35 2 jitter attenuation for 1hz@104uipp input 6 16 db 1-3,7,9-14,21-22,24,29,35 3 jitter attenuation for 10hz@20uipp input 12 22 db 1-3,7,9-14,21-22,24,29,35 4 jitter attenuation for 60hz@20uipp input 28 38 db 1-3,7,9-14,21-22,24,29,35 5 jitter attenuation for 300hz@20uipp input 42 db 1-3,7,9-14,21-22,24,29,35 6 jitter attenuation for 10khz@0.3uipp input 45 db 1-3,7,9-14,21-22,24,29,35 7 jitter attenuation for 100khz@0.3uipp input 45 db 1-3,7,9-14,21-22,24,29,35
MT9044 28 ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 2.048mhz input to 2.048 mhz output jitter transfer characteristics sym min max units conditions/notes? 1 jitter at output for 1hz@3.00uipp input 2.9 uipp 1-3,8,9-14,21-22,24,30,35 2 with 40hz to 100khz ?ter 0.09 uipp 1-3,8,9-14,21-22,24,30,36 3 jitter at output for 3hz@2.33uipp input 1.3 uipp 1-3,8,9-14,21-22,24,30,35 4 with 40hz to 100khz ?ter 0.10 uipp 1-3,8,9-14,21-22,24,30,36 5 jitter at output for 5hz@2.07uipp input 0.80 uipp 1-3,8,9-14,21-22,24,30,35 6 with 40hz to 100khz ?ter 0.10 uipp 1-3,8,9-14,21-22,24,30,36 7 jitter at output for 10hz@1.76uipp input 0.40 uipp 1-3,8,9-14,21-22,24,30,35 8 with 40hz to 100khz ?ter 0.10 uipp 1-3,8,9-14,21-22,24,30,36 9 jitter at output for 100hz@1.50uipp input 0.06 uipp 1-3,8,9-14,21-22,24,30,35 10 with 40hz to 100khz ?ter 0.05 uipp 1-3,8,9-14,21-22,24,30,36 11 jitter at output for 2400hz@1.50uipp input 0.04 uipp 1-3,8,9-14,21-22,24,30,35 12 with 40hz to 100khz ?ter 0.03 uipp 1-3,8,9-14,21-22,24,30,36 13 jitter at output for 100khz@0.20uipp input 0.04 uipp 1-3,8,9-14,21-22,24,30,35 14 with 40hz to 100khz ?ter 0.02 uipp 1-3,8,9-14,21-22,24,30,36 ac electrical characteristics - 8khz input jitter tolerance characteristics sym min max units conditions/notes? 1 jitter tolerance for 1hz input 0.80 uipp 1-3,6,9-14,21-22,24-26,28 2 jitter tolerance for 5hz input 0.70 uipp 1-3,6,9-14,21-22,24-26,28 3 jitter tolerance for 20hz input 0.60 uipp 1-3,6,9-14,21-22,24-26,28 4 jitter tolerance for 300hz input 0.20 uipp 1-3,6,9-14,21-22,24-26,28 5 jitter tolerance for 400hz input 0.15 uipp 1-3,6,9-14,21-22,24-26,28 6 jitter tolerance for 700hz input 0.08 uipp 1-3,6,9-14,21-22,24-26,28 7 jitter tolerance for 2400hz input 0.02 uipp 1-3,6,9-14,21-22,24-26,28 8 jitter tolerance for 3600hz input 0.01 uipp 1-3,6,9-14,21-22,24-26,28
MT9044 29 ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 1.544mhz input jitter tolerance characteristics sym min max units conditions/notes? 1 jitter tolerance for 1hz input 150 uipp 1-3,7,9-14,21-22,24-26,29 2 jitter tolerance for 5hz input 140 uipp 1-3,7,9-14,21-22,24-26,29 3 jitter tolerance for 20hz input 130 uipp 1-3,7,9-14,21-22,24-26,29 4 jitter tolerance for 300hz input 35 uipp 1-3,7,9-14,21-22,24-26,29 5 jitter tolerance for 400hz input 25 uipp 1-3,7,9-14,21-22,24-26,29 6 jitter tolerance for 700hz input 15 uipp 1-3,7,9-14,21-22,24-26,29 7 jitter tolerance for 2400hz input 4 uipp 1-3,7,9-14,21-22,24-26,29 8 jitter tolerance for 10khz input 1 uipp 1-3,7,9-14,21-22,24-26,29 9 jitter tolerance for 100khz input 0.5 uipp 1-3,7,9-14,21-22,24-26,29 ac electrical characteristics - 2.048mhz input jitter tolerance characteristics sym min max units conditions/notes? 1 jitter tolerance for 1hz input 150 uipp 1-3,8,9-14,21-22,24-26,30 2 jitter tolerance for 5hz input 140 uipp 1-3,8,9-14,21-22,24-26,30 3 jitter tolerance for 20hz input 130 uipp 1-3,8,9-14,21-22,24-26,30 4 jitter tolerance for 300hz input 50 uipp 1-3,8,9-14,21-22,24-26,30 5 jitter tolerance for 400hz input 40 uipp 1-3,8,9-14,21-22,24-26,30 6 jitter tolerance for 700hz input 20 uipp 1-3,8,9-14,21-22,24-26,30 7 jitter tolerance for 2400hz input 5 uipp 1-3,8,9-14,21-22,24-26,30 8 jitter tolerance for 10khz input 1 uipp 1-3,8,9-14,21-22,24-26,30 9 jitter tolerance for 100khz input 1 uipp 1-3,8,9-14,21-22,24-26,30 ac electrical characteristics - osci 20mhz master clock input characteristics sym min max units conditions/notes? 1 frequency accuracy (20 mhz nominal) -0 +0 ppm 15,18 2 -32 +32 ppm 16,19 3 -100 +100 ppm 17,20 4 duty cycle 40 60 % 5 rise time 10 ns 6 fall time 10 ns
MT9044 30 ? notes: voltages are with respect to ground (v ss ) unless otherwise stated. supply voltage and operating temperature are as per recommended operating conditions. timing parameters are as per ac electrical characteristics - timing parameter measurement voltage levels 1. pri reference input selected. 2. sec reference input selected. 3. normal mode selected. 4. holdover mode selected. 5. freerun mode selected. 6. 8khz frequency mode selected. 7. 1.544mhz frequency mode selected. 8. 2.048mhz frequency mode selected. 9. master clock input osci at 20mhz 0ppm. 10. master clock input osci at 20mhz 32ppm. 11. master clock input osci at 20mhz 100ppm. 12. selected reference input at 0ppm. 13. selected reference input at 32ppm. 14. selected reference input at 100ppm. 15. for freerun mode of 0ppm. 16. for freerun mode of 32ppm. 17. for freerun mode of 100ppm. 18. for capture range of 230ppm. 19. for capture range of 198ppm. 20. for capture range of 130ppm. 21. 25pf capacitive load. 22. osci master clock jitter is less than 2nspp, or 0.04uipp where1uipp=1/20mhz. 23. jitter on reference input is less than 7nspp. 24. applied jitter is sinusoidal. 25. minimum applied input jitter magnitude to regain synchronization. 26. loss of synchronization is obtained at slightly higher input jitter amplitudes. 27. within 10ms of the state, reference or input change. 28. 1uipp = 125us for 8khz signals. 29. 1uipp = 648ns for 1.544mhz signals. 30. 1uipp = 488ns for 2.048mhz signals. 31. 1uipp = 323ns for 3.088mhz signals. 32. 1uipp = 244ns for 4.096mhz signals. 33. 1uipp = 122ns for 8.192mhz signals. 34. 1uipp = 61ns for 16.384mhz signals. 35. no filter. 36. 40hz to 100khz bandpass filter. 37. with respect to reference input signal frequency. 38. after a rst or trst. 39. master clock duty cycle 40% to 60%. 40. prior to holdover mode, device was in normal mode and phase locked. 41. 1ulpp = 51ns for 19.44mhz signals.
package outlines plastic j-lead chip carrier - p-suf?x f d 1 d h e 1 i a 1 a g d 2 e e 2 dim 20-pin 28-pin 44-pin 68-pin 84-pin min max min max min max min max min max a 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) a 1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) d/e 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) d 1 /e 1 0.350 (8.890) 0.356 (9.042) 0.450 (11.430) 0.456 (11.582) 0.650 (16.510) 0.656 (16.662) 0.950 (24.130) 0.958 (24.333) 1.150 (29.210) 1.158 (29.413) d 2 /e 2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) e 0 0.004 0 0.004 0 0.004 0 0.004 0 0.004 f 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) g 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) h 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) i 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) for d & e add for allowable mold protrusion 0.010" e: (lead coplanarity) general-10
package outlines metric quad flat pack - l suf?x note: governing controlling dimensions in parenthesis ( ) are in millimeters. dim 44-pin 64-pin 100-pin 128-pin min max min max min max min max a - 0.096 (2.45) - 0.134 (3.40) - 0.134 (3.40) - 0.154 (3.85) a1 0.01 (0.25) - 0.01 (0.25) - 0.01 (0.25) - 0.00 0.01 (0.25) a2 0.077 (1.95) 0.083 (2.10) 0.1 (2.55) 0.12 (3.05) 0.1 (2.55) 0.12 (3.05) 0.125 (3.17) 0.144 (3.60) b 0.01 (0.30) 0.018 (0.45) 0.013 (0.35) 0.02 (0.50) 0.009 (0.22) 0.015 (0.38) 0.019 (0.30) 0.018 (0.45) d 0.547 bsc (13.90 bsc) 0.941 bsc (23.90 bsc) 0.941 bsc (23.90 bsc) 1.23 bsc (31.2 bsc) d 1 0.394 bsc (10.00 bsc) 0.787 bsc (20.00 bsc) 0.787 bsc (20.00 bsc) 1.102 bsc (28.00 bsc) e 0.547 bsc (13.90 bsc) 0.705 bsc (17.90 bsc) 0.705 bsc (17.90 bsc) 1.23 bsc (31.2 bsc) e 1 0.394 bsc (10.00 bsc) 0.551 bsc (14.00 bsc) 0.551 bsc (14.00 bsc) 1.102 bsc (28.00 bsc) e 0.031 bsc (0.80 bsc) 0.039 bsc (1.0 bsc) 0.256 bsc (0.65 bsc) 0.031 bsc (0.80 bsc) l 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) 0.029 (0.73) 0.04 (1.03) l1 0.077 ref (1.95 ref) 0.077 ref (1.95 ref) 0.077 ref (1.95 ref) 0.063 ref (1.60 ref) a 1 a index d 1 b e e 1 e pin 1 d a 2 notes: 1) not to scale 2) top dimensions in inches warning: this package diagram does not apply to the mt90810ak 100 pin package. please refer to the data sheet for exact dimensions. l l1 3) the governing controlling dimensions are in millimeters for design purposes ( )
package outlines note: governing controlling dimensions in parenthesis ( ) are in millimeters. dim 160-pin 208-pin 240-pin min max min max min max a - 0.154 (4.10) .161 (4.10) - 0.161 (4.10) a1 0.01 (0.25) 0.01 (0.25) 0.02 (0.50) 0.01 (0.25) 0.02 (0.50) a2 0.125 (3.17) 0.144 (3.67) .126 (3.20) .142 (3.60) 0.126 (3.2) 0.142 (3.60) b 0.009 (0.22) 0.015 (0.38) .007 (0.17) .011 (0.27) 0.007 (0.17) 0.010 (0.27) d 1.23 bsc (31.2 bsc) 1.204 (30.6) 1.360 bsc (34.6 bsc) d 1 1.102 bsc (28.00 bsc) 1.102 (28.00) 1.26 bsc (32.00 bsc) e 1.23 bsc (31.2 bsc) 1.204 bsc (30.6 bsc) 1.360 bsc (34.6 bsc) e 1 1.102 bsc (28.00 bsc) 1.102 bsc (28.00 bsc) 1.26 bsc (32.00 bsc) e 0.025 bsc (0.65 bsc) 0.020 bsc (0.50 bsc) 0.0197 bsc (0.50 bsc) l 0.029 (0.73) 0.04 (1.03) 0.018 (0.45) 0.029 (0.75) 0.018 (0.45) 0.029 (0.75) l1 0.063 ref (1.60 ref) 0.051 ref (1.30 ref) 0.051 ref (1.30 ref)
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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